As different operating voltages emerge for digital Integrated Circuits (IC), the need for logic level switching increasingly stands out. Level switching can vary with logic level, data bus form, or data transmitting rate. In certain examples, data bus form can include four-wire Serial Peripheral Interface (SPI), 32-bit parallel data bus, and the like. At present, there are a number of logic chips that can be used to control a Rail-to-Rail enabling signal. However, many of such logic chips stop operating when losing power, which may cause errors in the Rail-to-Rail enabling signal.
FIG. 1 illustrates an example of a circuit that can be used to control a Rail-to-Rail enabling signal, including Positive Channel Metal-Oxide-Semiconductor Field-Effect Transistors (PMOS) M1, M3, M5, M7, and M8, Negative Channel Metal-Oxide-Semiconductor Field-Effect Transistors (NMOS) M2, M4, M6, and M9, and resistors R1 and R2.
The PMOS M1 has a substrate and a source both connected to a power supply pwrin, a gate receiving an input signal in, and a drain connected to a drain of the NMOS M2 and to a gate of the PMOS M5. The NMOS M2 has a substrate and a source both connected to the power supply ground pwrn, a gate receiving an input signal in, and a drain connected to the drain of the PMOS M1 and to the gate of the PMOS M5.
The PMOS M3 has a substrate and a source both connected to the power supply pwrin, a gate receiving input signal in, and a drain connected to the resistor R1 and to a gate of the NMOS M6. The resistor R1 is connected, at one end, to the drain of the PMOS M3 and to a gate of the NMOS M6, and, at the other end, to a drain of the NMOS M4. The NMOS M4 has a drain connected to the resistor R1, a gate connected to a drain of the PMOS M5, a source connected to the power supply ground pwrn and a disabling signal providing node nrail, and a substrate connected to the power supply ground pwrn. The PMOS M5 has a substrate and a source both connected to the power supply pwrn, a gate connected to the drain of the PMOS M1 and to the drain of the NMOS M2, and a drain connected to the resistor R2, to the gate of the NMOS M4, to the drain of the PMOS M7, and to the gate of the PMOS M8. The resistor R2 is connected, at one end, to the drain of the PMOS M5 and to the gate of the NMOS M4, and, at the other end, connected to the drain of the NMOS M6. The NMOS M6 has a drain connected to the resistor R2, a gate connected to the drain of the PMOS M3, a source connected to the power supply pwrn and to the disabling signal providing node nrail, and a substrate connected to the power supply pwrn.
The PMOS M7 has a substrate and a source both connected to the power supply pwrn, a gate connected to an enabling signal providing node eni_rr, and a drain connected to the resistor R2, to the gate of the NMOS M4, to the drain of the PMOS M5, and to the gate of the PMOS M8. The PMOS M8 has a substrate and a source both connected to the power supply pwrin, a gate connected to the resistor R2, to the gate of the NMOS M4, to the gate of the NMOS M9, to the drain of the PMOS M5, and to the drain of the PMOS M7, and a drain connected to the enabling signal providing node eni_rr. The NMOS M9 has a gate connected to the source, to the power supply pwrn and to the disabling signal providing node nrail, a substrate connected to the power supply pwrn, a gate connected to the resister R2, to the gate of the NMOS M4, to the gate of the PMOS M8, to the drain of the PMOS M5 and to the drain of the PMOS M7, and a drain connected to the enabling signal providing node eni_rr. The gate of the PMOS M8 and the gate of the NMOS M9 are also connected to a signal gate.
In FIG. 1, when the voltage VCC of the power supply pwrin is normal, the enabling signal providing node eni_rr can output a corresponding Rail-to-Rail enabling control signal, such as the voltage VCC of the output power supply pwrin or the voltage Vnrail of the disabling signal providing node nrail, according to the high and low levels of the input signal in. When the power is down, the PMOS M3 and the PMOS M5 may not be in a stable state, which can cause the entire circuit to be unable to operate properly. As a result, the enabling signal output node eni_rr may be unable to reach the voltage Vnrail of the disabling signal providing node nrail, and thus may be unable to provide an accurate enabling control signal to equipment operated under the control of the enabling control.